1. Field of the Invention
The invention relates to refresh control and internal voltage generation in a semiconductor memory device.
2. Description of the Related Art
DRAM and SRAM are used as semiconductor memory devices. As is well known, DRAMs are cheaper and have a higher capacity than SRAMs, but must be refreshed. On the other hand, SRAMs need not be refreshed and are easier to use, but are more expensive and have a lower capacity than DRAMs.
A virtual SRAM (also termed a VSRAM or a PSRAM) is known as a semiconductor memory device that combines the advantages of a DRAM and an SRAM. A virtual SRAM includes a memory cell array that contains dynamic memory cells similar to those in a DRAM and has a built-in refresh controller, such that the refresh operation is performed internally. As a result, the external device (such as a CPU) connected to the virtual SRAM can access (read or write data to or from) the virtual SRAM without being aware of refresh operations. This feature of a virtual SRAM is known as “refresh transparency”.
The virtual SRAM is described in U.S. Pat. No. 6,545,943 B2 disclosed by the applicants, for example.
In order to retain data in each memory cell in a virtual SRAM, each memory cell must be refreshed once within a predetermined period. In the conventional art, one refresh operation is thus performed periodically for the memory cells in each row during each given refresh period.
Specifically, refresh execution for the memory cells in one row is requested in response to the generation of a periodic refresh timing signal issued from a refresh timer. The refresh operation for the memory cells of one row is carried out within one refresh period, i.e., within the period that ends at the generation of the next refresh timing signal, so as not to interfere with external access.
If refresh is carried out once during each refresh period, the period during which external access can be performed continuously is limited to one refresh period. This limitation is termed a “long cycle limitation”.
While the long cycle limitation described above exists in a virtual SRAM, there is no long cycle limitation in an SRAM. Therefore, researchers have sought to minimize the effect of this long cycle limitation in a virtual SRAM.
In the conventional semiconductor memory device, the internal voltage is normally generated in the semiconductor memory device using external voltage when power-on processing is executed. However, a drawback of the conventional art is that it takes a substantial amount of time for the internal voltage to reach a predetermined voltage level, i.e., for external access to become enabled.